TSMC Just Priced Its 2nm Wafer at $30,000. The Order Book Is Already Full Into 2028.

Thirty thousand dollars. That's roughly what a single 300-millimeter wafer costs on TSMC's newest 2-nanometer process, the silicon that will sit inside next year's flagship phones, servers, and AI accelerators. A year ago, the equivalent wafer on TSMC's 3-nanometer line ran closer to $25,000 to $27,000, depending on configuration and volume commitments. The jump to $30,000 turned out smaller than the 50% premium some analysts had penciled in for 2nm, but the absolute price still climbed to a new high, and the company selling these wafers has a waiting list stretching past 2027.

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What Changed

TSMC's N2 node is now in high-volume production at the company's Fab 20 site in Hsinchu, and the order book tells you most of what you need to know about demand. Lead times on N2 and its follow-on A16 process run 78 to 156 weeks, meaning a customer placing an order today might not see finished wafers until sometime in 2028. AMD has already gone public with the first major N2 product on the market: the Zen 6 generation EPYC "Venice" server chip, which began its production ramp in May and formally launched in July with 256 cores per socket. Apple is widely expected to follow with future iPhone and Mac silicon, though the company hasn't confirmed a node for its next generation of chips.

The pricing story doesn't stop at the wafer itself. Advanced packaging, the process that stacks memory and logic dies together into a finished AI accelerator, is arguably a tighter bottleneck than the wafer. TSMC's CoWoS packaging lines are booked solid, with lead times of 52 to 78 weeks, and total 2026 demand for CoWoS capacity has roughly tripled over two years to around 1 million wafers. Nvidia, which struck an exclusive chip supply arrangement with SpaceX earlier this month, alone holds an estimated 60% of that packaging capacity, close to 595,000 wafers, and its top three customers together control more than 85% of what's available.

Why It Matters

Every dollar TSMC adds to a wafer eventually shows up somewhere else. Margin pressure from rising component costs isn't a new story for the industry. Qualcomm made that case to investors already when it topped revenue estimates in early August and still watched its stock trade roughly 35% below May's high, with rising memory costs cited as a key drag on margin. Add pricier foundry wafers to that same equation and hardware margins face a second source of pressure, not a replacement for the first one.

TSMC's own numbers show the tension clearly. Second quarter revenue came in at $40.2 billion, up 36% from a year earlier, with chips built on 7-nanometer or smaller processes making up 77% of total wafer revenue. Gross margin hit 67.7% and operating margin hit 60.3%, both records for the company. But guidance for the third quarter calls for gross margin of just 65% to 67%, below what analysts had modeled near 67.5%, and executives have said the 2nm ramp alone will cut 3 to 4 percentage points off margin through the rest of the year. TSMC also lifted its 2026 capital spending plan to a range of $60 billion to $64 billion, well above the $52 billion to $56 billion it had guided to previously. The company is spending more to build capacity, charging more for what comes out of it, and still telling investors that margins will dip before they recover.

Pulse24 has been tracking the broader question of whether AI buildout costs are inflationary or deflationary, and a $30,000 wafer that customers are still lining up to buy reads as a fresh data point on the inflationary side of that ledger, even if this particular price hike came in milder than feared.

What to Watch Next

Third quarter earnings from AMD, Qualcomm, and eventually Apple should show how much of the higher wafer cost gets passed through to device and server prices versus absorbed into margin. TSMC's own margin trajectory over the next two quarters matters too: if gross margin stabilizes above 65% despite the 2nm ramp, that's a sign the transition is being managed well. N2 wafer output is the other thing worth tracking. TSMC's Hsinchu site alone is ramping toward roughly 30,000 wafers a month, and the company's combined 2nm fabs in Hsinchu and Kaohsiung are targeting more than 60,000 wafers a month by the end of 2026. CoWoS packaging capacity is expanding on a similar timeline, from around 80,000 wafers a month currently toward a 2026 target near 130,000. If both ramps hold, the twin bottlenecks in wafers and packaging should ease into 2027. A slip in either would make Nvidia's dominant packaging share an even bigger flashpoint with the customers standing behind it in line.

The Pulse24 Take

Wafer prices rarely make headlines the way earnings beats or Fed decisions do, but they sit upstream of almost everything happening in this cycle. A $30,000 price tag on the industry's most advanced process, booked solid into 2028, is a clean signal that AI-driven demand for leading-edge silicon hasn't cooled, even as some AI-adjacent credit and valuation stories elsewhere have gotten shakier. TSMC clearly has the pricing power to raise wafer costs and still book capacity solid through 2028. A separate and murkier question is whether the companies buying that capacity, and the investors pricing their stocks on AI growth, have fully modeled what happens to margins once those wafers hit cost of goods sold next year.